integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. h 06/26/08 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. is62c1024al is65c1024al description the issi is62c1024al/is65c1024al is a low power, 131,072-word by 8-bit cmos static ram. it is fabricated using high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce1 is high or ce2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using cmos input levels. easy memory expansion is provided by using two chip enable inputs, ce1 and ce2. the active low write enable (we) controls both writing and reading of the memory. functional block diagram 128k x 8 low power cmos static ram features ? high-speed access time: 35, 45 ns ? low active power: 100 mw (typical) ? low standby power: 20 w (typical) cmos standby ? output enable (oe) and two chip enable (ce1 and ce2) inputs for ease in applications ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 5v (10%) power supply ? commercial, industrial, and automotive tem- perature ranges available ? standard pin confguration: 32-pin sop/ 32-pin tsop (type 1) ? lead free available a0-a16 ce1 oe we 128k x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 ce2 july 2008
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. h 06/26/08 is62c1024al is65c1024al truth table mode we ce1 ce2 oe i/o operation v dd current not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x high-z i sb 1 , i sb 2 output disabled h l h h high-z i cc read h l h l d out i cc write l l h x d in i cc pin configuration 32-pin sop pin descriptions a0-a16 address inputs ce1 chip enable 1 input ce2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output v dd power gnd ground pin configuration 32-pin tsop (type 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd v dd a15 ce2 we a13 a8 a9 a11 oe a10 ce 1 i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we ce2 a15 v dd nc a16 a14 a12 a7 a6 a5 a4 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 operating range (is65c1024al) range ambient temperature v dd automotive -40c to +125c 5v 10% operating range (is62c1024al) range ambient temperature v dd commercial 0c to +70c 5v 10% industrial -40c to +85c 5v 10%
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. h 06/26/08 is62c1024al is65c1024al absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to +7.0 v t stg storage temperature C65 to +125 c p t power dissipation 1.0 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 5.0v. dc electrical characteristics (over operating range) symbol parameter test conditions options min. max. unit v oh output high voltage v dd = min., i oh = C1.0 ma 2.4 v v ol output low voltage v dd = min., i ol = 2.1 ma 0.4 v v ih input high voltage 2.2 v dd + 0.5 v v il input low voltage (1) -0.5 0.8 v i li input leakage gnd v in v dd com. -1 1 a ind. -2 2 auto. -5 5 i lo output leakage gnd v out v dd com. -1 1 a ce1 = v ih , or ind. -2 2 ce2 = v il , or oe = v ih or auto. -5 5 we = v il note: 1. v il (min.) = -0.3v dc; v il (min.) = -2.0v ac (pulse width -2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width -2.0 ns). not 100% tested.
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. h 06/26/08 is62c1024al is65c1024al read cycle switching characteristics (1) (over operating range) -35 ns -45 ns symbol parameter min. max. min. max. unit t rc read cycle time 35 45 ns t aa address access time 35 45 ns t oha output hold time 3 3 ns t ace 1 ce1 access time 35 45 ns t ace 2 ce2 access time 35 45 ns t doe oe access time 10 20 ns t lzoe (2) oe to low-z output 3 5 ns t hzoe (2) oe to high-z output 0 10 0 15 ns t lzce 1 (2) ce1 to low-z output 3 5 ns t lzce 2 (2) ce2 to low-z output 3 5 ns t hzce (2) ce1 or ce2 to high-z output 0 10 0 15 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.6 to 2.4v and output loading specifed in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. is62c1024al/is65c1024al power supply characteristics (1) (over operating range) -35 ns -45 ns symbol parameter test conditions min. max. min. max. unit i cc average operating ce1 = v il , ce 2 = v ih com. 25 ma current v in = v ih or v il , ind. 30 i i/o = 0 ma, f=0 auto. 35 i cc 1 v dd dynamic operating v dd = max., ce1 = v il com. 30 ma supply current i out = 0 ma, f = f max ind. 35 v in = v ih or v il auto. 40 ce2 = v ih typ. (2) 20 i sb 1 ttl standby current v dd = max., com. 1 ma (ttl inputs) v in = v ih or v il , ce1 v ih , ind. 1.5 or ce2 v il , f = 0 auto. 2 i sb 2 cmos standby v dd = max., com. 5 a current (cmos inputs) ce1 v dd C 0.2v, or ind. 10 ce2 0.2v, v in v dd C 0.2v, auto. 45 or v in v ss + 0.2v, f = 0 typ. (2) 4 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. h 06/26/08 is62c1024al is65c1024al data valid t aa t oha t oha t rc dout address ac waveforms read cycle no. 1 (1,2) ac test conditions parameter unit input pulse level 0.6v to 2.4v input rise and fall times 5 ns input and output timing 1.5v and reference level output load see figures 1a and 1b ac test loads 1838 100 pf including jig and scope 993 output 5v 1838 5 pf including jig and scope 993 output 5v figure 1a. figure 1b.
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. h 06/26/08 is62c1024al is65c1024al write cycle switching characteristics (1,3) (over operating range, standard and low power) -35 ns -45 ns symbol parameter min. max. min. max. unit t wc write cycle time 35 45 ns t sce 1 ce1 to write end 25 35 ns t sce 2 ce2 to write end 25 35 ns t aw address setup time to write end 25 35 ns t ha address hold from write end 0 0 ns t sa address setup time 0 0 ns t pwe (4) we pulse width 25 35 ns t sd data setup to write end 20 25 ns t hd data hold from write end 0 0 ns t hzwe (2) we low to high-z output 10 15 ns t lzwe (2) we high to low-z output 3 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.6 to 2.4v and output loading specifed in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce1 low, ce2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tested with oe high. notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce1 = v il , ce2 = v ih . 3. address is valid prior to or coincident with ce1 low and ce2 high transitions. read cycle no. 2 (1,3) t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzce address oe ce1 ce2 dout
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. h 06/26/08 is62c1024al is65c1024al write cycle no. 2 ( ce1 , ce2 controlled) (1,2) notes: 1. the internal write time is defned by the overlap of ce1 low, ce2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe = v ih . ac waveforms write cycle no. 1 ( we controlled) (1,2) data-in valid data undefined t wc t sce1 t sce2 t aw t ha t pwe (4) t hzwe high-z t lzwe t sa t sd t hd address ce1 ce2 we dout din high-z data undefined data-in valid t wc t sce1 t sa t ha t sce2 t pwe (4) t aw t hzwe t sd t hd t lzwe address din ce1 ce2 we dout
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. h 06/26/08 is62c1024al is65c1024al data retention switching characteristics symbol parameter test condition min. typ. max. unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 2.0v, ce1 v dd C 0.2v com. 5 a or ce2 0.2v ind. 10 v in v dd C 0.2v, or v in v ss + 0.2v auto. 45 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note: 1. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. data retention waveform ( ce1 controlled) data retention waveform (ce2 controlled) vdd ce1 vdd - 0.2v t sdr t rdr v dr ce1 gnd 4.5v 2.2v data retention mode vdd ce2 0.2v t sdr t rdr v dr 0.4v ce2 gnd 4.5v 2.2v data retention mode
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. h 06/26/08 is62c1024al is65c1024al ordering information: is62c1024al commercial range: 0c to +70c speed (ns) order part no. packa ge 35 is62c1024al-35q plastic sop 35 is62c1024al-35t tsop, type 1 industrial range: C40c to +85c speed (ns) order part no. package 35 is62c1024al-35qi plastic sop 35 is62c1024al-35qli plastic sop, lead-free 35 is62c1024al-35ti tsop, type 1 35 is62c1024al-35tli tsop, type 1, lead-free ordering information: is65c1024al automotive range: -40c to +125c speed (ns) order part no. package 45 is65c1024al-45qa3 plastic sop 45 is65c1024al-45qla3 plastic sop, lead-free 45 is65c1024al-45ta3 tsop, type 1 45 is65c1024al-45tla3 tsop, type 1, lead-free
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